Palo Alto Sr Principal ASIC Design Verification Engineer NetSec 

United States, California 

557985597

Being the cybersecurity partner of choice, protecting our digital way of life.

Your Career

As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug. You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation.

Your Impact

• Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification
• Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies
• Develop flows, methodologies, and infrastructure for emulation - Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers
• Define new tools and methodologies to continuously improve quality and velocity
• Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification

Your Experience

• BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred
• Minimum 5 years experience in ASIC design verification
• Demonstrated success in taking multiple ASIC products from concept to mass production
• Expertise in SystemVerilog and UVM
• Technical strength in the following areas is required
  • Defining test plans, including comprehensive adversarial testing
  • Developing rich functional coverage models
  • Creating powerful and scalable test benches
  • Implementing sophisticated self-checking infrastructure with reference models and scoreboards
  • Developing reusable constrained-random tests
  • Debugging failures
  • Closing coverage
• Experience in the following areas is preferred
  • Networking and cyber security
  • Formal property verification
  • Silicon validation - bringup, test, debug, and regression
  • Creating models in Python and C/C++
  • Writing driver code in C
• Skilled in writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing
• Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status
• Strong leadership, collaboration, and communication skills

We define the industry instead of waiting for directions. We need individuals who feel comfortable in ambiguity, excited by the prospect of a challenge, and empowered by the unknown risks facing our everyday lives that are only enabled by a secure digital environment.

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $235000 - $260000/YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found .

All your information will be kept confidential according to EEO guidelines.