Microsoft Senior DDR Subsystem Verification Engineer 

Taiwan, Taoyuan City 

551920709

Intelligent Cloud

Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
• 4+ years of pre-silicon subsystem or IP verification experience.
• 3+ years of DDR subsystem verification experience.
• 1+ years of DDR PHY intergrating or verifying experience

Preferred Qualifications

• Demonstrated experience in verifying memory controller, DDR PHY, and/or at DDR sub-system level including integration verification of memory controller IP with DDR PHY and Electronic Design Automation (EDA) vendor sourced Dual In-line Memory Module (DIMM) Verification IP (VIP)
• Deep understanding of JEDEC spec including mode registers, timing parameters, refresh operations, initialization, calibration, training, power management, and error handling.
• Experience with verification for a full product cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
• Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking
• Aptitude for writing scripts/software with industry standard languages like Python
• Experience applying generative AI to day-to-day tasks

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until July 25th, 2025.

• Own or lead verification of one or more aspects/features of a memory controller Intellectual Property (IP) and/or Double Data Rate (DDR) subsystem integration with Physical Layer (PHY)
• Learn about the design and interact with partner teams to define verification strategies and test plans
• Develop verification environments and run and debug simulations to drive quality
• Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
• Innovate to improve verification efficiency through methodologies or tools
• Apply industry leading generative AI solutions to verification work
• Coach and mentor others in your areas of expertise
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion