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Apple Experienced AMS Design Verification Engineer m/f/d Austria, Upper Austria, Linz 551905550
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Minimum Qualifications
- Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
- Hands-on experience with constrained random verification environments
- Basic design background in support of verification results analysis
- Knowledge of Object Oriented Programming (OOP)
- Proficiency in English language is required
Preferred Qualifications
- Master´s degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
- Hands-on experience with Assertion Based Verification
- Familiarity with system design using C++, Python or Verilog
- Familiarity with FPGA emulation platforms
- The minimum salary pursuant to the applicable collective bargaining agreement amounts to €79.204 gross per year for full time employment. Actual salaries are oriented at current market salaries and take your qualifications and experience into account.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
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