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Tesla Sr DFT Engineer Dojo 
United States, Texas, Austin 
551780045

23.06.2024
What You’ll Do
  • Define and implement various DFT features at RTL and gates using in-house flows

  • Work closely with the physical design team in achieving design closure with DFT features

  • Perform block-level scan insertion, ATPG, coverage analysis, and simulations

  • Run top-level test pattern retargeting and simulations

  • Identify design changes needed for improving test coverage

  • Work with test / product engineering team members on test pattern delivery and Si bring up

What You’ll Bring
  • Knowledge of Testability techniques and features (Compressed Scan, Built-in-Self-Test, Loop-Back, Boundary Scan) covering digital logic domain, embedded memories and PHY/IO’s

  • Well versed in JTAG / 1500 / 1687 networks. BSDL, ICL and PDL knowledge preferable

  • Expertise in ATPG, coverage analysis, and zero-delay / SDF-based pattern simulations. Experience with Cadence DFT tools (Modus and Genus) or Mentor DFT tools (Tessent Shell) preferred

  • Good knowledge of Verilog, logic design, circuit design fundamentals as well as timing

  • Working knowledge of TCL, python (or another scripting language like Perl)

  • Experience in implementation of MBIST and knowledge of repair schemes, algorithms is a plus

  • Experience or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST, loop-backs etc..) is a plus

  • Post Silicon experience in Pattern conversion for Testers, Pattern Bring-up & Debug, Silicon Characterization etc. is a plus

  • Degree in Computer Engineering or Electrical Engineering or equivalent experience with evidence of exceptional abilities