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Google Lead ASIC DFT Engineer United States, California, Mountain View 545218272
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 8 years of experience in DFT or physical design.
- Experience with scan insertion, Automatic Test Pattern Generation (ATPG), gate level simulations and silicon debug, low power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow.
- Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.
- Experience with IJTAG Instrument Connectivity Language (ICL), Procedural Description Language (PDL) terminology, ICL extraction, ICL modeling with Siemens Tessent Tool.
- Experience with Spyglass-DFT, DFT Scan constraints and evaluating Static Timing Analysis (STA) paths.
- Experience with a scripting language such as Perl or Python.
- Knowledge of high performance design DFT techniques like Streaming Scan Network (SSN), High-Bandwidth IJTAG.
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