Cisco ASIC DFT Product Lead 

United States, Oregon, Portland 

385464914

The application window is expected to close on 3/28/2025

Your Impact

You will be in the Silicon One development organization as an ASIC DFT Product Lead in San Jose, CA with a primary focus on Design-for-Test and Product qualification activities

Key Responsibilities:

• Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL, post silicon validation flows.
• Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
• The job requires the candidate to have the ability to craft solutions and drive cross functional and external vendor interactions

Minimum Qualifications:

Preferred Qualifications:

• Verilog design experience – developing custom DFT logic & IP integration; Experience leveraging functional verification routines for DFT DV.
• DFT CAD development & EDA interactions – Test Architecture, Methodology and Infrastructure
• Background in Test Static Timing Analysis with Test Constraint signoff ownership a plus..
• Past experience with Post silicon validation using DFT patterns and product engineering.
• Have participated in multiple tapeouts and silicon bringup activities.