Microsoft Senior Quantum Engineer - Cryo-CMOS Digital Circuit Design 

Taiwan, Taoyuan City 

544958305

Microsoft Quantum has assembled a talented and diverse international team to create the world’s first scalable quantum computing system. Our full-stack approach involves exciting innovations from physics on the quantum plane to providing global quantum services. The Microsoft Quantum program strives to fundamentally change the world of computing to help solve humankind’s currently unsolvable problems. We are on the cusp of an accelerated effort in quantum computing.

This position offers an opportunity to have a meaningful influence on a revolutionary technology. The research effort includes a diverse staff of theoretical and experimental physicists, hardware designers and software engineers around the world. We are looking for a

Microsoft's mission is to empower every person and every organization on the planet to achieve more. At Microsoft Quantum, we aim to empower science and scientists to solve the world's biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence, and quantum information technology.

Required/minimum qualifications:

• Doctorate inElectrical Engineering, Computer Engineering, Computer Science, or related fieldAND 1+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position
  • OR Master's Degree inElectrical Engineering, Computer Engineering, Computer Science, or related fieldAND 4+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree inElectrical Engineering, Computer Engineering, Computer Science, or related fieldAND 6+ years experience in industry or in a research and development environment
  • OR equivalent experience.
• Experience in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, CDC/Lint closure synthesis, floorplanning, place and route timing constraint, and post-silicon debug.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. § 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:

• Doctorate inElectrical Engineering, Computer Engineering, Computer Science, or related fieldAND 3+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position
  • OR Master's Degree inElectrical Engineering, Computer Engineering, Computer Science, or related fieldAND 6+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree inElectrical Engineering, Computer Engineering, Computer Science, or related fieldAND 8+ years experience in industry or in a research and development environment
  • OR equivalent experience.

The successful candidate will have the following qualifications:

• 7+ years of related technical engineering experience
• 4+ years of experiencein digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, CDC/Lint closure synthesis, floorplanning, place and route, timing constraint, and post-silicon debug

Desired Skills:

• 10+ years of industry experience in logic design delivering complex solutions.
• Successful Application-Specific IntegratedCircuit(ASIC) tape outs in deep sub-micron technologies.
• Good background in debugging designs as well as simulationenvironment.
• Knowledge of verification principles, testbenches, Universal Verification Methodology (UVM), and coverage.
• Experience with Logic design/Register Transfer Level (RTL) entry
• Experience in RTL to GDS implementation in Physical Design domain, from synthesis to place and route of partitions through all signoffs including timing signoff, physical verification, EMIR signoff, and Low Power Verification.
• Deep experience with EDA software fordigital design(Cadencesuite).
• Experience/exposure to low-temperature circuit design and measurements isdesirable.
• Knowledge of quantum physics, behaviour of semiconductors at cryogenic temperatures is desirable.
• Effective team collaborator and proficient communication skills.
• Ability to be flexible and adapt to new situations in a rapidly changing research environment.
• Demonstrated experience with report writing and documentation.

Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until July 25, 2025.

This role involves deep, technical work in a small, collaborative environment. We are looking for someone who is as passionate about their own contribution as they are to empowering and inspiring others. The candidate willbe responsible forcontributing to the technical direction of the research based on system and block design ideas and simulations, experimental results, program needs and the input from cross-functional colleagues.

Key Responsibilities include:

• Contribute to the architecture, specification, design, test,and development ofCryoCMOSfunctions and ASICs to support the full-stack quantum hardware implementations.
• Be responsible for
  • Logic design/Register Transfer Level (RTL) entry
  • RTL to GDS implementation in Physical Design domain,from synthesis to place and route of partitions through all signoffsincluding timing signoff, physical verification, EMIR signoff, and Low Power Verification.
  • Define and implement efficient UVM-based verification environments and use them toverify+testdigital designs
  • Test plan,testsand infrastructure to complete formal validation of complex design and report bug/issues
  • Effective team collaboratorthat will work closely with theanalog,architecture,andcryogenicsteams tooptimizetradeoffs within the design.

• Conduct cryogenic and room temperature measurements of the ASICs and perform analysis and reporting of the measurement results.

• Use lab best practices and protocols.

• Work in accordance with health and safety policies and take care that your actions do notimpacton the health and safety of yourself or others.

• Ensure hazards and risks areidentifiedand controlled for within your area of responsibility.

Other:

• Embody our and