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Cisco ASIC Engineering Technical Leader United States, California, San Jose 54243628
18.11.2024
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What You'll Do
The Core Hardware Business Unit is looking for a motivated Senior Verification engineer/lead to engage in new development of our UCS family. You will have an ASIC design and verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume semiconductor markets.
- Architect block, cluster and top level DV environment infrastructure
- Create DV infrastructure from scratch for block, cluster and top level environments
- Maintaining existing DV environments and enhancing them
- Ensuring complete verification coverage through implementation and review of code and functional coverage
- Working closely with designers
- Supporting tests done with emulation
- Work closely with software teams and debug issues found during firmware development
- Responsible for ASIC bring up
- 10+ years ASIC design verification experience with aBachelor’s or Master’s degree in equivalent experience
- Prior experience in Asic verification using UVM/System Verilog.
- Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
- Prior experience with Perl and/or Python scripting
- Prior domain experience on one or more protocols – PCIe, Ethernet, RDMA, TCP
Preferred Qualifications
- Prior experience with Forwarding logic/Parsers/P4
- Prior experience with Veloce/Palladium/Zebu/HAPS
- Formal verification experience with (iev/vc formal)
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