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Google ASIC Design Verification Engineer Machine Learning University Graduate United States, California, Sunnyvale 542060488
01.04.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
- Academic, educational, internship, or project experience designing or verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog for FPGAs, ASICs, or SOCs.
- Experience coding in SystemVerilog or Verilog.
Preferred qualifications:
- Master's or Doctorate degree in Electrical Engineering or related field.
- Experience with verification methodology such as UVM/OVM/VMM.
- Experienced with the full verification life cycle.
- Knowledge of SystemVerilog.
- Strong problem solver, communicator, and team player.
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