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Google Signoff Circuit Methodology Engineer India, Karnataka, Bengaluru 525552301
22.07.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 5 years of experience in physical design.
- 5 years of experience in static timing analysis, circuit/signoff methodology and simulation.
- Experience in one or more sign-off convergence in Static timing analysis (STA) electrical checks and physical verification domains.
Preferred qualifications:
- Experience in using Static Timing Analysis (STA), power grid network delivery, and power analysis tools.
- Experience in timing signoff for SoCs or designs with multiple voltage/clock domains.
- Experience with Exploratory Data Analysis (EDA) tools for implementation and signoff, Physical Design, Static Timing Analysis (STA) and Electromigration and IR drop (EMIR) analysis.
- Experience in automation with programming in TCL, Python, Perl and the knowledge of Speed path debug or correlation studies.
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