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Google Signoff Design Methodology Engineer Silicon India, Karnataka, Bengaluru 43277303
22.07.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Computer Science, IT, a related field, or equivalent practical experience.
- 5 years of experience with static timing analysis, synthesis, physical design & automation.
- Experience in physical design tool automation such as synthesis, P&R and sign-off tools.
Preferred qualifications:
- Experience in extraction of design parameters, Quality of Results metrics, and analyzing data trends.
- Knowledge of timing constraints, convergence and signoff.
- Knowledge of parasitic extraction tools and flow.
- Knowledge of Register-Transfer Level (RTL) languages (e.g., Verilog/SystemVerilog).
- Knowledge of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR) and PDV signoff methodologies.
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