Qualcomm Memory Controller Design Engineer 

United States, California, San Diego 

492381752

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers. The front end of the DDR controller interfaces to the rest of the system such as CPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products.

The candidate will work on architecture, design, and deployment of the Memory Controllers for the LPDDR/PCDDR technologies into QCT products. You will develop or contribute to the development of design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will also participate in C/C++ modeling of memory controller IP. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.

Experience with the following:

• DDR controller architectures especially the front end interfacing to the CPU, DSP, and multimedia processors

• Experience with x86 or ARM CPU/bus architectures

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$92,000.00 - $138,000.00