Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent practical experience.
4 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
4 years of experience in ARM-based SoCs, interconnects and ASIC methodology.
Preferred qualifications:
Master’s degree in Electrical Engineering or Computer Engineering.
Experience in cross-domain, including domain validation, design for testing, physical design, and software.
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).