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Apple RTL Design Engineer United States, Oregon, Beaverton 489479337
28.03.2024
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Key Qualifications
- Extensive knowledge of mixed signal concepts
- Relevant and proven experience of RTL design, Verilog and SystemVerilog
- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
- Validated experience with synthesis, static timing, DFT, is a plus
- Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus
- Knowledge of scripting languages. Perl and Python are plusses
- Strong communication, collaboration and presentation skills
Description
In this role, you will assist with specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing substantial assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Education & Experience
BS degree in technical discipline with minimum 10 years of relevant experience.
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