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Apple RTL Design Engineer United States, Oregon, Beaverton 489479337
06.06.2024
Description
In this role, you will assist with specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing substantial assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
Key Qualifications
- Extensive knowledge of mixed signal concepts
- Relevant and proven experience of RTL design, Verilog and SystemVerilog
- Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
- Validated experience with synthesis, static timing, DFT, is a plus
- Proven knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus
- Knowledge of scripting languages. Perl and Python are plusses
- Strong communication, collaboration and presentation skills
Education & Experience
BS degree in technical discipline with minimum 10 years of relevant experience.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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