IBM System Verilog Designer 

United States, Texas, Houston 

489174638

Document and Design RTL code to integrate into the larger design
Work with Design Verification team and update UVM test cases to fully test designs
Utilize lab environment to validate designs and review boards and debug issues
Responsibilities spanning all phases of the FPGA engineering life-cycle, including requirements analysis, design, meet performance targets and code development, verification, and integration
Execute, analyze and enhance Verification results and coverage
Experience with Xilinx FPGA’s and their development tools and development environments
Digital design methodologies including synthesis, verification, implementation and timing analysis
Agile development
Python experience