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IBM Senior System Verilog Designer United States, Texas, Houston 241126230
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Your Role and Responsibilities
We need fast, focused design engineers to adjust with the changing environment while following best practices for high quality and sustainable code. We need engineers ready to take on the challenges of design and verification for their blocks and the system.
• Responsibilities spanning all phases of the hardware engineering life-cycle, including requirements analysis, design, code development, verification, integration and performance targets
• Design System Verilog code and integrate IP into the larger design
• Work with Design Verification team on UVM benches to fully test designs
• Utilize lab environment to validate designs and review boards and debug issues
• Hands-on design and lab experience with PCIe, AXI and more
• Document the low-level design specifications
• Participate, engage, and enhance verification efforts
Required Technical and Professional Expertise
• 5+ years of Experience with Verilog and/or System Verilog development
• UVM experience
• Bachelor’s degree in Computer Engineering, Electrical Engineering, related discipline
• Exposure in digital design, ASICs and FPGAs
• Strong communication skills
• Demonstrated experience working with a team
• Self-starter and work independently
Preferred Technical and Professional Expertise
• Experience with Xilinx FPGA’s
• Digital design methodologies including synthesis, verification, implementation and timing analysis
• Experience with Assertions
• Agile development
• Python experience
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