Qualcomm Senior ASIC Designer – ML/AI Video Processor IP 

Canada, Ontario, Markham 

486291741

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field.

Principal Duties

• Develop micro-architecture specifications by applying sound ASIC engineering practices

• Design and System-C modelling of multimedia and compute ASIC modules and sub-systems

• Implement modules in hardware design languages such as System Verilog RTL and Catapult HLS

• Resolve performance, area, power and system cost tradeoffs to optimize micro-architectures

• Create performance verification monitors, models, and test scenarios

• Design tests and functional models using System-C, Python, and System Verilog

• Complete test plan reviews and coverage-driven constrained-random verification

• Develop SVA assertions for functional and formal verification

• Integrate modules into a sub-system, performing code and test quality checks

• Implement and debug constraints to achieve netlist synthesis and static timing closure

Minimum Qualifications:

• Bachelors or master’s degree in Engineering or Engineering Science

• 2+ years’ ASIC development experience

• Legally permitted to work on-site in Canada

Preferred Qualifications:

• Proven experience delivering Verilog and System Verilog RTL

• Detail oriented with strong analytical and debugging skills

• Strong communication (written and verbal), collaboration, and specification skills

• Experience with cache control and/or video processing function design and/or verification

• Practiced design knowledge working with some of the following concepts:

• Clock domain crossing and reset architecture

• Image processing filter implementation

• FIFOs implementation/integration

• Bus implementation/verification techniques

• Memory selection and control

• High speed and low power design optimization

• Bus interface protocols (APB, AHB, AXI)

• Experience with some of the following

• Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)

• Model development (SystemC, or C++)

• Design rule and CDC checking (SVA assertions, Spyglass, 0-in, etc.)

• Scripting languages (PERL, Python, TCL, C, etc.)

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.