Qualcomm Senior Staff/ASIC Design Lead Low Power AI Subsystems 

Canada, Ontario, Markham 

337015719

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Push the boundaries on features and performance.

Qualcomm Technologies Audio products are designed to offer premium wireless connectivity, high levels of integration, immersive sound quality, and on-device AI for smart audio and context aware applications. An ultra-low power subsystem within a low power SoC; a chip-within-a-chip HW block incorporating multiple always-on IP's, design execution within this group requires solving ground-breaking challenges and multiple power domain crossing issues.

Responsibilities will include:

• Design high speed, low power digital hardware solutions

• Contribute to definition, micro-architecture and documentation

• Collaborate closely with the Verification team to test, debug and close coverage on the design

• Evaluate synthesis results to verify the design meets the speed, power and area targets

• Support internal hardware integration, SW teams around the world

• Resolve architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision

• Use of various design tools (VCS, DC, Linting, CDC, LEC, CLP etc.) to check and improve design quality

• Provide ideas and further the innovation of ASICs, IP cores, and process flows

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Requirements:

• Expert ASIC hardware design and/or implementation experience.

• Expertise with Verilog/VHDL RTL design languages and advanced ability to write clean, readable, synthesizable RTL.

• Deep understanding of ASIC/VLSI concepts

• Experience in logic synthesis using Synopsis and/or Cadence tools

Preferred Qualifications:

• Min 6+ years of extensive ASIC hardware design experience

• UPF experience

• Expertise with power analysis, power modeling and low power RTL design.

• Expertise with clock domain crossing techniques

• Expertise with a subset of DC, FC, PTPX, Power Compiler, Primetime, Modeltech, VCS, power theatre, etc.)

• Expertise with design rule check (Spyglass, etc.), Formal verification (Formality, LEC, etc.) and/or Power analysis and simulation

• Scripting skills (Python , PERL, TCL or C)

• Expertise spanning bus interface protocols (APB, AHB, AXI)

• Experience with post-silicon debug nice to have

• Experience with UVM nice to have

• Experience with automotive safety concepts and standards such as ISO26262 nice to have

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.