Microsoft Senior IP RTL Design Engineer 

United States, Oregon, Hillsboro 

484312915

Required Qualifications:

• 7+ years of related technical engineering experience

  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting).
• Proficient in Verilog/System Verilog coding constructs.

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:
  • This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Master's degree in Electrical Engineering or BS in Computer/Electrical Engineering with 2+ years of experience.
• Experience with Industry standard interface protocols such as AXI, APB, etc.
• Experience with ARM Fabric IPs.
• Experience with IPXACT.
• Understanding of Computer Architecture fundamentals
• Ability to write scripts using Python, Tcl, Perl etc.
• Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
• Proficiency with UPF (Low power intent).
• Proficiency in clock crossing techniques.
• Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
• Applied understanding of low power design principles.
• Understanding in design closure challenges in power and clock domain crossings.
• Experience writing timing constraints, exceptions, and clock constraints; good understanding in SDC commands and TCL constraints.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until August 13, 2024.

• Own subsystem integrating several industry standard IPs.
• Specifying and micro-architecting digital blocks, and performing concept studies to guide performance, power, and gate count.
• Write RTL code for blocks based on architectural specifications.
• Participate in the design verification and bring-up of such blocks by writing substantial assertions, debugging code, and otherwise interacting with the design verification team.
• Assess and then refine the implementation for area, power, and performance.
• Define, create, and maintain project documentation, including design documents with analysis reports.
• Collaborate with architecture, subsystem owners, and IP providers to configure the IP to maximize performance for various use cases.
• Grow your micro-architectural knowledge of your own blocks as well as other blocks in the SoC.
• Describe the power intent of the design through UPF.
• Perform design quality checks such as Lint, CDC, RDC, Low Power Intent, Synthesis, Logic Equivalence.
• Understand Dataflow and Clocking requirements and drive solutions for timing critical paths.
• Automate tasks using scripting for efficiency.
• Delight your customers who receive your deliverable by providing high quality functional block on schedule and with professional integrity.
• Collaborate with highly energetic cross functional team members with respect and with One Microsoft mentality to establish synergies.
• Challenge the status quo with a growth mindset.
• Embody our