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Google RTL Design Engineer Core-IP India, Karnataka, Bengaluru 307332749
14.04.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
- 3 years of experience designing RTL digital logic using SystemVerilog for ASICs or equivalent experience
- Experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP)
- Experience with a scripting language such as Perl or Python
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science
- 6 years of experience designing RTL digital logic using SystemVerilog for ASICs or equivalent experience
- Experience in area, power and performance design optimization
- Experience in design and development of security or audio blocks
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