Cisco ASIC Design Verification Engineer 

Taiwan, Taipei, Taipei 

476798164

Who You Are

You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, hands-on experience in System Verilog and UVM methodology, with basic knowledge of C++, scripting, as well as ASIC design and verification flow.

You’ll be part of Cisco Common ASIC Group, focusing on developing various test benches and contributing to different aspects of verification infrastructure.

Responsibilities Include:

• Designing UVM/SystemVerilog testbenches.
• Defining new DV methodologies.
• Enhancing existing testbenches.
• End-to-end verification of various design blocks.
• Contributing to top level verification.
• Be a part of emulation testing efforts.
• Participate in the ASIC bring-up

Education and Experience Required:

• Bachelor’s or master’s degree in EE and CE.
• 3+ years of ASIC Design Verification

Minimum Qualifications

• Collaborative and team-focused, with the drive to learn and grow
• Hands-on experience on System Verilog and UVM methodology
• Ability to construct testbench including scoreboard, agents, sequencers, and monitors
• Ability to debug issues independently
• Proficient in constrained random DV environments
• Good written and verbal communication skills

Preferred Qualifications

• Good Scripting experience (Python, Perl, TCL, shell programming) is a plus
• Knowledge on latest high speed Ethernet protocol and packets is a plus.

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)