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Google ASIC RTL Engineer III Silicon IP/Subsystem Israel, Tel Aviv District, Tel Aviv-Yafo 46797848
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Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
- Experience with design sign off and quality tools (e.g., Lint, CDC, etc.).
- Experience with SOC architecture.
- Experience in logic design.
Preferred qualifications:
- Master's degree or PhD in Computer Science or a related technical field.
- Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate (DDR), Advanced Extensible Interface (AXI), or Advanced RISC Machines (ARM) processors family.
- Knowledge of high performance and low power design techniques.
- Knowledge of assertion-based formal verification.
- Excellent problem-solving and debugging skills.
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