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What You Can Expect
Design IP that includes but not limited to 112G/56G PAM4; 32G PAM2; DDR; Die-to-Die High Speed Interconnect; System PLL IPs.
Provide the instructions to the layout engineers.
Working with the AE for the IP characterization and validation plan.
Supporting IP Lab characterization and debugging.
What We're Looking For
Master’s degree with 5+ years of related professional experience and/or PhD in Electrical Engineering with 3+ years of experience.
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