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The Role:
In this role you will:
• Design advanced L1/L2 algorithms and solutions for the Kuiper communication system.
• Work with ASIC development teams to build power/area efficient L1/L2 HW accelerators to be integrated into Kuiper SoCs.
• Provide specifications and work with implementation teams on the development of embedded L1/L2 HW/SW architectures.
• Work with multi-disciplinary teams to develop advanced solutions for time, frequency and spatial acquisition/tracking in LEO systems, particularly under large uncertainties.
• Develop link-level and system-level simulators and work closely with implementation teams to evaluate expected performance and provide quick feedback on potential improvements.
• Develop proof-of-concepts for critical communication payload components using SDR platforms consisting of FPGAs and general-purpose processors.
• Develop testbeds consisting of digital, IF and RF components while accounting for link-budgets and RF/IF line-ups. Previous experiences with VSAs/VSGs, channel emulators, antennas (particularly phased-arrays) and anechoic chamber instrumentation are a plus.
• Work with development teams on system integration and debugging from PHY to network layer, including interfacing with flight computer and SDN control subsystems.
• Willing to work in fast-paced environment and take ownership that goes from algorithm specification, to HW/SW architecture definition, to proof-of-concept development, to testbed bring-up, to integration into the Kuiper system.
• Be a team player and provide support when requested while being able unblock themselves by reaching out RF, ASIC, SW, Comsys and Testbed supporting teams to move forward in development, testing and integration activities.
• Ability to adapt design and test activities based on current HW/SW capabilities delivered by the development teams.Export Control Requirement:
• Master’s degree in Electrical Engineering, related discipline, or equivalent experience
• 7+ years professional experience working in wireless communications at the system or implementation level.
• Deep understanding of Multiple access systems such as OFDMA, TDMA, CDMA, etc.
• In depth experience of modem L1/L2 algorithms development and architectures.
• Experience in the development of link and system level simulators using Matlab/Python/C++.
• Broad spectrum of knowledge to be able to understand end-to-end network system architecture from wireless physical layer all the way up to application end-point.
• Experience in test setup automation using Matlab/Python/Pearl.
• Experience with current software development processes and tools including Agile, TDD, BDD, CI, Git.
• Must have the ability to work in a small team and drive to go beyond expectations to deliver results.
• Ideal candidate has a wireless communication systems or digital signal processing background, a passion for building real-world carrier-grade communication systems, and industry experience developing PHY/MAC layer HW/SW targeting SoCs, FPGAs, and general-purpose processors.
• Experience with leading technical initiatives and key deliverables.
• PhD with emphasis in broadband wireless or wireline communication systems.
• In depth understanding and use of communication theory and digital signal processing, particularly related to topics such as time-frequency synchronization and channel acquisition in previous experience.
• Experience in HW/SW co-design to achieve power/area efficient solutions to be integrated into heterogeneous/distributed computing architectures consisting of SoCs, FPGAs and general-purpose processors.
• Experience with software defined radios (SDRs) and embedded programming in C/C++ and VHDL/Verilog is a plus.
• Experience with lab test equipment such as channel emulator, spectrum analyzers and signal and network traffic generators.
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