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Microsoft Principal Hardware Engineer 
Taiwan, Taoyuan City 
42313979

25.09.2025

a trustedengineers to help achieve that mission.

the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal,Systems Engineering (CHSE)and industry knowledge to envision and implement future technical solutions that will manage andthe Cloud infrastructure.

Required Qualifications:

  • Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 7+ years technical engineering experience
    • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience
    • OR equivalent experience.
  • 7+ years of relevant experience in system (compute, storage, networking, and/or accelerator) level design and/or implementation across the hardware development lifecycle.
  • 7+ years of hands-on experience in server hardware architecture, design, and developmentwith solid understanding of hardware, firmware, and Operating System (OS).


Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings

This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

  • Proven experience in AI and GPU system development, including design, validation, and deployment at scale.
  • Ability to work across multiple disciplines (hardware, firmware, software, and/or data center infrastructure) toidentify
  • Broad technicalexpertiseacross electrical, mechanical, thermal, power, signal integrity, and system security domains.
  • Deep understanding of high-volume silicon (SoCs, GPUs, FPGAs),compute, storage, and networking systems, including manufacturing and deployment.
  • Hands-on experience with high-speed interfaces such as PCIe, DDR, and Ethernet, and familiarity with system firmware (BIOS, BMC) and OS-level integration (Windows and/or Linux).
  • Proven background in datacenter-scale operations and infrastructure, including system-level debugging and root cause analysis.
  • Demonstrated ability to manage hardware programsthroughthe full product lifecycle, from concept to production.
  • Familiarity with AI training and inference workloads, and the ability to evaluate system designs based on TCO, performance per watt, and performance per dollar.
  • Excellent communication and collaboration skills, with the ability to lead cross-functional teams and influence technical direction.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Responsibilities
  • Lead end-to-end product delivery from concept through launch, ensuring technical excellence andtimelyexecution.
  • Drive cross-functional technical decision-making across architecture, silicon, firmware, hardware, OS, validation, and manufacturing teams.
  • Define and manage program baselines in partnership with TPMs, including scope, schedule, budget, and change control.
  • Ownqualityof design deliverables and ensure alignment with system-level requirements and performance goals.
  • Influence platform, rack, and datacenter-level solutions for next-generation AI infrastructure.
  • Evaluate and de-risk NUDD (New, Unique, Different, Difficult) technologies and features through structured analysis and mitigation planning.
  • Collaborate with internal and externalpartners—including open-sourcecommunities—to integrate innovative technologies seamlessly.
  • Articulate architecturaland designtradeoffs across electrical, mechanical, thermal, and cost dimensions tooptimize forTCO, performance, and scalability.
  • Work closely with validation engineering team, systems engineering team and manufacturing engineering team to drive issues found during test to closure