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What You Will Be Doing:
Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems.
Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers.
Define Memory module, Package, and PCB layouts appropriate to the system workloads
Debug and bring up memory evaluation / validation and failure issues on memory technology.
Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology.
What We need to see:
Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience)
10 years of proven track record in DRAM design, module design, or memory sub system design.
Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM.
Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY.
Experience in the design, bring-up and validation for memory failure analysis
Experience with Python, C/C++ for development and memory workload analysis.
Strong user documentation and interpersonal skills
You will also be eligible for equity and .
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