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What you'll be doing:
Full custom circuit design involving memory arrays like multi-port register files, SRAMs, and/or caches, for performance critical IPs like CPUs/GPUs.
Have to perform transistor level circuit and logic design, spice verification, schematic entry and coordination with layout team.
Ability to understand architectural specifications and develop custom SRAM circuits which meet stringent performance, area and power requirements.
Ability to close design to the specs by running various flows like EM, IR, Noise, static timing analysis.
Develop state of the art flows for timing, EM/IR or other verification needs.
Develop variation tolerant circuits in advanced technologies like 7nm and below.
What we need to see:
BE/M-Tech in Electrical & Electronics, or equivalent experience.
5+ Years of relevant experience in SRAM Design / Circuit design
Have sound fundamentals in CMOS devices, basics of VLSI design and really good timing concepts involving dynamic and sequential circuits.
Prior experience is required with Cadence virtuoso environment, hspice simulations, variation analysis and transistor level design.
Proficiency in Perl/Python or equivalent scripting language is a requirement.
Prior exposure to some form of memory design (like SRAMs or register files) will be a huge advantage.
Experience in advanced technology nodes like 16/7 nanometers is a huge plus.
Prior exposure with circuit flow development will be helpful.
Good interpersonal skills, Should be an excellent teammate.
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