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What You'll Be Doing:
Full custom circuit design involving memory arrays like multi-port register files, SRAMs, and/or caches, for performance critical IPs like CPUs/GPUs
Design cutting-edge SRAM circuits using state-of-the-art technology processes
Optimize circuits for performance, area, and power
You will have to perform transistor level circuit and logic design, spice verification, schematic entry and coordination with layout team
Ability to understand architectural specifications and develop custom SRAM circuits which meet stringent performance, area and power requirements
Ability to close design to the specs by running various flows like EM, IR, Noise, static timing analysis
Develop state of the art flows for timing, EM/IR or other verification needs
Develop variation tolerant circuits in advanced technologies like 7nm and below
Improve/develop flows, methodologies and automation to accelerate various design closure, data collection, and analysis, further ensure working silicon
What We Need To See:
You would need to have sound fundamentals in CMOS devices, basics of VLSI design and really good timing concepts involving dynamic and sequential circuits
Prior experience is required with Cadence virtuoso environment, hspice simulations and transistor level design or design-optimization
Proficiency in Perl/Python or equivalent scripting language is a plus
Prior exposure to some form of memory design (like SRAMs or register files) will be a huge advantage
Experience in advanced technology nodes like 7/5 nanometers is a huge plus
Good interpersonal skills, should be an excellent teammate
BE/M-Tech or equivalent experience in Electrical & Electronics or equivalent
5+ yrs of experience
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