In this role, core responsibilities include, but are not limited to the following:•Develop accurate and simulation-efficient analog behavioral models for Analog/RF blocks in SystemVerilog.• Build and reuse real-numbered analog behavioral models of the Analog and Mixed-Signal Circuits.•Verify that the behavioral models are accurate representations of corresponding analog circuits.•Review specifications and collaborate with the design team to extract features, define, and execute models’ development/validation plans.•Build and reuse monitors and checkers for RF, Mixed-Signal, and Digital blocks.•Debug failures, fix testbench/model/checker issues, manage bug tracking, etc.•Write scripts for automation of the flow and improve Mixed-Signal verification methodology.•Develop top/block-level Mixed-Signal and Digital testbenches and generate directed/ constrained random tests in a UVM framework.