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Apple Mixed Signal Modeling/Verification Engineer United States, Texas, Austin 148621053
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Development of RNM RF/Analog models in System Verilog.Develop models with self-checking techniques.Assess required model accuracy level depending on verification goals.Develop appropriate assertions to enforce analog/digital specs are respected and provide digital verification passing criteria.Work with Analog designers setting up AMS simulation environment.Debug complex chip digital-on-top testbenches and seek root causes for failures.
- BSEE required.
- Strong fundamentals in circuit nodal analysis.
- Basic fundamentals in analog circuit concepts/topologies.
- Familiarity with basic logic building blocks and HDL language like verilog.
- Experience in RNM coding in SystemVerilog.
- Experience working with Cadence mixed signal verification environment.
- Ability to read analog schematics and extract related main functionality.
- MSEE or beyond is preferred.
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