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Apple Mixed Signal Modeling/Verification Engineer United States, Texas, Austin 148621053
18.11.2024
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Description
Development of RNM RF/Analog models in System Verilog.Develop models with self-checking techniques.Assess required model accuracy level depending on verification goals.Develop appropriate assertions to enforce analog/digital specs are respected and provide digital verification passing criteria.Work with Analog designers setting up AMS simulation environment.Debug complex chip digital-on-top testbenches and seek root causes for failures.
Minimum Qualifications
- BSEE required.
- Strong fundamentals in circuit nodal analysis.
- Basic fundamentals in analog circuit concepts/topologies.
- Familiarity with basic logic building blocks and HDL language like verilog.
Preferred Qualifications
- Experience in RNM coding in SystemVerilog.
- Experience working with Cadence mixed signal verification environment.
- Ability to read analog schematics and extract related main functionality.
- MSEE or beyond is preferred.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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