Microsoft Sr Test Design Verification Engineer 

United States, Texas, Austin 

396280274

cutting edgehigh-performance Azure cloud servers, clients,and augmented realityto innovative consumer products like Xbox.

enior Design VerificationESilicon Manufacturing Packaging

Required/Minimum Qualifications:

· 7+ years of related technical engineering experience

o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

• 7+ years of experience in design verification with experiencedelivering complex SoC.
• 7+ years of experience in debugging (Verilog) designs as well as simulation and/or emulation environments.

Other Requirements:

to meet Microsoft, customer and/or government security screening requirementsfor this role. These requirementsinclude, butare not limited to the following specialized security screenings:

• requiredto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred/Additional Qualifications:

• Experience with Joint Test Action Group (JTAG/Test Access Port (TAP) debuginterfaces.
• In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based testenvironments.
• Experience with scripting language such as Python or PerlorTcl/Tk.
• Experience inglobal SOCareaslikeBoot,JTAG,Clocking, Resets, Security, fusesetc.
• Understanding of SoC architecture.
• Experience interacting with 3rdparty vendor on IP definition and sign-off.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until June 28, 2024.

STeam isa computer/electrical engineer to deliver premium-quality designs once considered impossible. Weare responsible for, custom Intellectual Property (IP) and System-on-Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner.

• Working across design,verification,

• Create and enhance constrained-random verification environments usingSystemVerilogand Universal Verification Methodology (UVM).

• Analyse and debug test failures with designers to deliver functionally correct design.

• and write functional coverage for stimulus and corner cases.

• Develop, audit & execute the IP/Subsystem SoC level verificationplan.

• Close coverage to plug verification holes and meet tape out requirements.

• with the product engineering teams on the delivery of manufacturing test patterns&assistwith silicon bring-up.

Embody our and