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What You’ll Be Doing:
Responsible for defining test plans & architecting testbenches for verification of the CPU/GPU memory subsystem.
Verifymicro-architecture/architecturefeatures at subsystem or full chip testbenches.
Work with architects, designers, and pre-silicon verification teams to accomplish your tasks.
Build reusable bus functional models, traffic generators, monitors, checkers and scoreboards following coverage driven verification methodology.
Developing innovative tools/automation to stress the design under test and cover the verification space.
What We Need To See:
BE/BS or MTech/MS inelectrical/electronicsengineering or computer engineering or equivalent experience
2+ years of experience working on ASIC development
Exposure to micro-architecture of high-performance CPU or GPU memory subsystems
Expose to industry standard verification methodologies
Ways To Stand Out From The Crowd:
Exposure to coherency protocols, cache verification and network-on-chip (NOC)
Exposure to CPU memory subsystem and knowledge of AMBA/CHI protocols.
Innovative mindset, ability to use automation/tools to cover vast verification spaces.
Good communication skills and ability collaborate across multiple teams.
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