Intel SoC Design Verification Engineer 

India, Karnataka, Bengaluru 

489384982

Job Description

• In this role, the candidate will be part of a team that defines and develops methodology and executes SoC Validation for IP/SoC Server designs at Intel.
• Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.
• Finds and implements corrective measures to resolve failing tests.
• Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology.
• Absorbs learning from post silicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.

Qualifications

• Candidate needs to have Masters degree (M.Tech./MS) with atleast 3 years of relevant working experience in the area of RTL Methodology, RTL/Gate Level Simulation, Validation and Debug.
• Bachelor degree (BE/B.Tech.) with atleast 5 years of relevant working experience in the area of RTL Methodology, RTL/Gate Level Simulation, Validation and Debug.
• The candidate is expected to have hands-on work experience in the areas of RTL Level Simulation and Validation with good knowledge on Test Benches.
• Strong hands-on technical knowledge of Verilog/System Verilog language syntax, System Verilog Assertions, RTL Simulation and Debug concepts using industry standard tools is a must.
• Able to debug tests independently with Architects, Design Engineers and SD/PD (FCT) Engineers.
• Able to validate a given design in Zero Delay, Timing and Power Aware mode.
• Work with stake holders on securing input collaterals, tracking timelines and converge the Val signoff for a design.
• Understanding of Formal Equivalence Verification concepts, exposure to SoC integration methodologies/design style will be an added advantage.
• Scripting skills with PERL/TCL, Unix exposure and strong communication (both verbal and written) are desired.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits