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Apple Verification Student SoC Group - Jerusalem Site Israel, Jerusalem District, Jerusalem 383696623
30.05.2024
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Description
In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are encouraged to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop a verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, and de-bug the test failures. Develop block, IP, and SoC level test benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal design.
Key Qualifications
- - Experience in SoC verification is an advantage
- - Familiarity with verification environments, UVM, and SystemVerilog – an advantage
- - Knowledge of formal, hardware acceleration – an advantage
- - Scripting and programming experience using several of the following: Perl, e, Verilog, SystemVerilog, C, C++, and TCL
Education & Experience
- Student of Computer science and Electrical engineering with 4 semesters till graduation
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