In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are encouraged to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop a verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, and de-bug the test failures. Develop block, IP, and SoC level test benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal design.