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Google Physical Design Verification Engineer Silicon 
Taiwan, New Taipei 
378345215

24.06.2024

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience with physical design verification flows and methodology (e.g., DRC, LVS, PERC, ESD signoff, ERC, antenna, DFM) using industry standard signoff tools.
  • Experience managing various physical verification check runsets.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
  • Experience on full chip physical verification and bring up on physical verification methodology for correct by construction strategies.
  • Experience on physical verification signoff of a SOC/sub-systems/SSWRPs.
  • Experience with physical signoff verification tools (e.g., calibre and ICV).
  • Experience scripting with Tcl, Perl, or Shell.