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What you'll be doing:
Mixed-Signal/Analog circuit design for High-Speed Memory I/O Interfaces
Solve challenges of circuit designs in the latest CMOS FinFET processes
Take designs through productization and be actively involved in all stages of development
Work with multi-functional teams to optimize the design
What we need to see from you:
MS/PhD in Electrical Engineering or equivalent experience
The candidate has 5+ years of well-rounded high-Speed DRAM (LPDDR4/5, DDR4/5, GDDR5/6, HBM2/3) or other SerDes interface related design experience.
In-depth understanding of deep submicron CMOS FinFET process and related circuit design issues
Familiarity with device reliability, ESD, and Latch-Up requirements
Possess an understanding of system-level timing budgets, specs, and analysis
Working Knowledge of the package substrate, board design, and power delivery is a plus.
Strong background of Cadence custom design tools, various circuit simulators like Hspice, XA, FineSim, Spectre
Knowledge of Verilog, Nanotime, Matlab, or similar tools is a plus
Hands-on experience of silicon debug with Lab test and measurement equipment is a plus
A teammate with good interpersonal skills
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