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Intel Power Integrity Engineer United States, Texas 375221044
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This Power Integrity Engineer position involves research, pathfinding, implementation, analysis, validation and sign-off of power distribution network (PDN) including monolithic and heterogenous SoCs, package substrate, PCB and VRM. You will work with multi-functional teams to drive the development of advanced droop mitigation schemes, develop PI methodology and automation, quantify benefits of various circuit schemes through end-to-end PDN simulations, provide design guidelines and requirements to platform, package and SoC/IP teams ensuring robust integrations.
Additional areas of responsibility for this role include, but not limited to the following:
- Develop and analyze power delivery networks including 2D and 3D model extraction and noise analysis across die/C4 bumps, silicon, package, sockets, and boards
- Collaborate with the silicon integration team, die floor planners, package and PCB design teams to optimize the on-die decoupling partitions and implement the package/PCB decoupling scheme and voltage regulation for package/die
- Define power grid specification and power and area targets to achieve the best balance of power integrity and performance
- Derive platform level specifications from silicon specifications, ensure package/platform pathfinding to converge on feature set/form factor, and VR performance, characterization
- Performs measurements to characterize power noise profile across frequency, ground bounce, and other key metrics to verify power delivery network after design and correlate back to pre-silicon models
- Adhere to project timelines and deliver high-quality work within specified deadlines
Qualifications:
You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
- Bachelor's degree with 5+ years, masters with 3+ years of experience in Electrical or Computer Engineering or related field, which must include:
- Knowledge of Silicon, Package and PCB PDN design practices
- Good understanding of various droop mitigation schemes, Verilog level modeling, On-chip PDN and circuit techniques
- Expertise in circuit simulation with Spice, ADS and EM extractions with commercially available solvers from Ansys, Cadence, Synopsys and Keysight
- Scripting skills in Python/tcl
Preferred Qualifications:
- Design, modeling and analysis experience of on-chip droop mitigation, LDO techniques, die/package/PCB PDN
- Experience with transmission line theory and electromagnetic field theory
- Package and PCB design tools from Cadence and Mentor
- Power converter topologies and control schemes
- PhD in Electrical or Computer Engineering or related field.
Position of Trust
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
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