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Cisco ASIC Design/DV Engineer China, Shanghai 368262401
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Who You'll Work With
What You'll Do
1. Design and implement complex ASICs.
2. Participate in the architecture definition, implementation and verification phases for our products.
3. Help create detailed design specifications and test plans.
4. Design and implement block level RTL, perform synthesis and achieve timing closure goal.
5. Develop test benches and create test cases
6. Work with cross-functional teams (hardware, software, diagnostics and signal integrity).
7. Assist in complex subsystem level lab bring-up, integration, and unit test verification.
8. China customer enablement on pre-sales, system development, SDK/ASIC validation.
Who You Are
1. 1 ~ 3 relevant experience with knowledge on UVM, Verilog, SystemVerilog, C, C++
2. Skillful at utilizing Verilog/System Verilog in complex logic designs
3. Able to create clean code, using the best practices of software design
4. Knowledge of Unix and a scripting tool is a plus
5. Knowledge on networking is a plus
6. Proficient in both written and verbal English/Mandarin.
7. Self-motivation, teamwork and strong communication skills are essential
Educational Background
Master of Science in EE/CS or related field.
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