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Google Senior CPU Formal Verification Engineer Taiwan, New Taipei 364446110
20.02.2025
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
- Experience with hardware description languages like System Verilog and VHDL
- Experience with full cycle of design verification: plan, env/test developing, bug/cov closure.
Preferred qualifications:
- Master’s degree in Electrical Engineering, Computer Science, or related field.
- ISS (instruction set simulator) based CPU DV experience, developing ISA model such as RISC-V spike model or ARM ASL based simulators.
- Experience in verifying CPU design based on RISC-V, ARM or x86.
- Practical experience in establishing formal verification to multiple design blocks. Ability to strategically handle constraints and deal with tool capacity issues by abstraction.
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