ARM Modelling Engineer 

Sweden 

359654711

DDR Subsystem Architect is a technical role responsible for hardware architecture of LPDDR, DDR, HBM and GDDR subsystems for high-volume, sophisticated, SoC platforms on groundbreaking process nodes across multiple market segments including mobile, automotive, datacenter and networking, and IoT.

• Consume JEDEC specs and DRAM vendor roadmaps to create product intercept roadmaps.
• Work with SoC architects, business-units, and customers to establish & reconcile DDR subsystem features & requirements.
• Author architectural specifications to a mature stage allowing design and implementation teams to engage actively.
• Work with IP vendors to draft, negotiate, and execute SoWs/contracts.
• Work with design, verification, and validation teams to draft and review design specifications & test-plans (pre & post silicon), and support execution teams as required.
• Debug performance and functional issues with high-level models, RTL simulation, hard and soft IP.

• Deep understanding of DDR controller design and memory types (LPDDR, DDR, HBM, GDDR).
• Experience with controller-to-PHY interface protocols (DFI).
• Familiarity with Arm bus protocols such as APB, AXI, CHI, CXS, etc.
• Experience with performance/QoS, RAS, security, power-management, debug, and test features in the context of DDR subsystems.
• Bachelor's or Master’s degree in Electrical or Computer Engineering with minimum 10 years of experience in a senior development position.
• Excellent presentation, interpersonal, written, and verbal communication skills.

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