Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
3 years of experience in physical design.
Experience in one or more sign-off convergence in Static timing analysis (STA) electrical checks and physical verification domains.
Expertise in high-performance, low-power physical design and implementation techniques with industry standard implementation and signoff tools.
Preferred qualifications:
3 years of industry experience with high-performance CPUs.
Experience in using Static Timing Analysis (STA), power grid network delivery, and power analysis tools.
Knowledge of Central Processing Unit (CPU) including critical iterations for timing and low power microarchitecture and implementation techniques for CPUs.
Knowledge of computer architecture, logic design, RTL and Knowledge of Verilog/SystemVerilog.