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Google Coherent Memory System Architect Silicon 
United States, California, Mountain View 
335437294

09.07.2025
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience in micro-architecture and design of ASIC blocks.
  • Experience in designing/implementing Register-Transfer Level (RTL) for one or more blocks: Central Processing Units (CPUs), Graphics Processing Units (GPUs), Caches, Memory Management Units (MMUs) or Coherent Fabrics.
  • Experience in micro-architecture/design performance analysis, tools, and simulators.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience in building build time configurable designs.
  • Knowledge in one or more of these areas, Coherent Interconnects, Caches, Memory Systems.
  • Knowledge of Hardware Description Languages (HDL) such as System verilog, Verilog.