Facebook ASIC Engineer Design 

India, Karnataka, Bengaluru 

286727295

Participate in Micro-architecture, Design, and Verification reviews and provide feedback.

Design and develop RTL or HLS code for some of the IPs.

Analyze designs and enhance PPA (Power, Performance, Area).

Support and develop Verification Infrastructure, analyze and improve Verification Coverage.

Support Simulation accelerators and post-Silicon validation.

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, Electronics Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.

Exposure to Micro-architecture development.

Exposure to RTL development using Verilog, System Verilog or HLS.

Knowledge of Computer Architecture and Logic Design fundamentals.

Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment.

Currently has, or is in the process of obtaining, a Masters degree in Electrical Engineering, Computer Engineering or related engineering fields.

Experience in data path development.

Experience in HLS.

Experience with Lint, CDC, Synthesis, & Power Optimization.

Experience with High Performance Computing.

Scripting capability with Python or Perl.