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What you will be doing:
Work with system architects to understand the functional and performance requirements of a unit or feature.
Define micro-architecture and develop RTL for owned unit and/or feature.
Work with verification and physical design teams to ensure that the unit or feature is accurately verified and implemented.
Own silicon bring-up in conjunction with post silicon validation and SW teams.
Mentor junior engineers and guide them in their work.
What we need to see:
BS / MS or equivalent experience.
2+ years of experience.
Proven knowledge in implementation of complex features or units.
Expertise in micro architecture definition, RTL coding using Verilog or System Verilog.
Expertise in using design and verification tools (Synthesis, lint, VCS or equivalent simulation tools, debug tools like Debussy, GDB).
Experience in memory management unit, interconnect design and cache controller design desirable.
Good debugging and problem solving skills. Scripting knowledge.
Good interpersonal skills and ability & desire to work as a teammate are a huge plus.
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