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Cisco ASIC Verification Engineer United States, California, San Jose 285956882
12.06.2024
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Who You'll Work With
You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross functional teams to verify the ASIC in simulation, in emulation and during ASIC bring up.
What You'll Do
- Maintaining existing DV environments and enhancing them
- Construct testbench including scoreboard, agents, sequencers, and monitors for new blocks
- Write test plan, develop testcases, debug regression failures and drive to module verification closure
- Ensuring complete verification coverage through implementation and review of code and functional coverage
Who You Are
- You are an ASIC Design Verification Engineer with 5+ years of related work experience with a Bachelor’s or Master degree.
- You will have an ASIC design verification background with hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume semiconductor markets.
Minimum qualifications
- Hands-on and deep understanding of System Verilog and UVM methodology
- Experience in verifying complex blocks, clusters and top level for SoC
- Can build testbenches from scratch, hands on experience with System Verilog constraints, structures and classes.
- Ability to debug issues independently
- Proficient in functional coverage and constrained random DV environments.
- Scripting skills: Perl and/or Python scripting
- Strong domain experience in one or more protocols in a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
- Experience with Veloce/HAPS is a plus
- Formal verification (iev/vc formal) knowledge is a plus
Preferred skils
- Strong domain experience in one or more protocols in a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
- Experience with Veloce/HAPS is a plus
- Formal verification (iev/vc formal) knowledge is a plus
- Post silicon bring up and debug in lab skill is a plus
We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).
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