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What you will be doing:
Partnering closely with physical design and timing closure designers to understand and optimize hardware design performance and engineering productivity in a broad range of domains across RTL analysis, floorplanning, clocking, constraints, timing and power optimization, and final signoff.
Inventing high performance C++ and Python software that can automatically pinpoint VLSI concerns and opportunities early in the physical design process and integrating it with flexible automation to maximize designer efficiency.
Researching and innovating scalable methods for VLSI data gathering coupled with intuitive analysis and visualization tailormade to enable NVIDIA's leading performance, power, area, schedule, and yield targets.
In general, developing algorithms, tools, and methodologies to predict and improve performance and reliability beyond what industry standard tools can offer alone.
What we need to see:
Master’s Degree in Electrical Engineering, Computer Engineering, or equivalent work experience
5+ years of relevant work experience
Deep understanding of backend design process, especially static timing analysis and early physical design, such as floorplanning.
Expertise in coding -- preferably in C++ and/or Python
Strong communication and interpersonal skills
Ways to stand out from the crowd:
Mix of both software and hardware design experience.
Experience in physical design optimization and automation algorithms.
Experience with data visualization and GUIs is helpful.
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