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Google Memory Subsystem Architect Silicon 
Taiwan, New Taipei 
261388652

14.08.2024

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 3 years of experience in ASIC performance power management or low-power design and methodology.
  • Experience in computer architecture concepts, such as micro-architecture, cache, pipe-lining, and memory subsystems.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
  • Experience designing, implementing, or validating in two or more areas such as Coherent fabrics, Caches, Fabrics, IOMMUs, QoS, or Memory Systems.
  • Experience in SoC architecture performance analysis, tools, and simulators (e.g., Cycle Accurate, TLM, or Functional).
  • Experience with C or C++.
  • Experience in SoC system pre-silicon or post-silicon performance analysis and tuning.
  • Knowledge of HDL languages such as System Verilog, Verilog.