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Intel DFT Design Engineer Taiwan, Taiwan Province, Hsinchu 231343054
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Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block. Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.
As a Frontend IP design engineer, you will be involved in architecting, implementing and verifying digital IP.
The core activities to be handled are: Understanding SoC requirement, translating them into IP specifications, RTL coding, RTL verification, Running static checks, IP packaging and delivery to SoC.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.The ideal candidate should exhibit the following attributes:
Strong communication skill
Team work skill
Engineering knowledge and expertise
Good written/oral communication skills and self-driven.
Minimum qualificationThe candidate must possess a bachelor's in computer science, electrical engineering, or equivalent degree on related fields.
4+ years of work experience in RTL design and/or RTL verification using UVM
Minimum 1 year of working experience in ATE
2+ years of work experience with Spyglass/VC (CDC/DFT/LINT)
2+ years of experience with any of the following scripting/programming languages: TCL/Python/PERL
Experience in leading IP implementation
Preferred qualifications include:
2+ years of experience with DFT/DFX
Good understanding of GITHUB and CI/CD techniques
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